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| Datasheet File OCR Text: |
| ETHERNET LAN CONTROLLER --TOP VIEW-- 108 105 100 95 90 85 80 75 w w a D . w aS t ee h 4U t .c om DEC21143-TD (1/4) IL08 73 109 110 72 70 115 65 120 125 130 135 140 144 w w w t a .D 5 10 S a 15 e h 20 U t4 e 30 .c m o 60 55 50 45 40 37 1 25 35 36 w w w .D ta a he S t4 e U om .c DEC21143-TD (2/4) PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 PIN NO. 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 PIN NO. 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 I/O -- -- -- O O O O -- I I I I I O I I -- -- I -- I O I/O I/O I/O -- I/O I/O I/O -- I/O I/O I/O I -- -- -- -- I/O I/O I/O -- I/O I/O I/O -- I/O I/O SIGNAL VCC VCC GND TP TD__ TP TD_ TP TD+ TP TD++ VCC TP RD+ TP RD_ TCK TMS TDI TDO INT L RST I GND VCC PCI CLK VCC CLAMP GNT L REQ L AD31 AD30 AD29 VCC AD28 AD27 AD26 GND AD25 AD24 C BE L3 IDSEL GND VCC VCC GND AD23 AD22 AD21 GND AD20 AD19 AD18 VCC AD17 AD16 I/O I/O I/O I/O I/O -- -- I/O I/O I/O O/D I/O I/O I/O I/O -- I/O I/O I/O -- I/O I/O I/O -- -- -- -- I/O I/O I/O I/O -- I/O I/O I/O -- I/O I/O I/O O O O I/O I/O I/O I/O -- -- I/O SIGNAL C BE L2 FRAME L IRDY L TRDY L GND VCC DEVSEL L STOP L PERR L SERR L PAR C BE L1 AD15 AD14 GND AD13 AD12 AD11 VCC AD10 AD9 AD8 GND VCC VCC GND C BE L0 AD7 AD6 AD5 VCC AD4 AD3 AD2 GND AD1 AD0 CLKRUN L BR CE L BR A0/CB PADS L BR A1 BR AD7 BR AD6 BR AD5 BR AD4 GND VCC BR AD3 I/O SIGNAL I/O BR AD2 I/O BR AD1 I/O BR AD0 I/O GEP0/AUI BNC I/O GEP1/ACTIV I/O GEP2/RCV MATCH/WAKE GEP3/LINK I/O GND -- XTAL2 O XTAL1 I VCC -- IREF I ACVCC -- VCAP H I ACVCC -- SR DO I SR DI O SR CK O SR CS O GND -- MII CRS/SD I MII CLSN/SYM RXD4 I MII/SYM TXD3 O MII/SYM TXD2 O MII/SYM TXD1 O MII/SYM TXD0 O O MII TXEN/SYM TXD4 MII/SYM TCLK I VCC -- GND -- I/O MII RX ERR/SEL10 100 MII/SYM RCLK I MII DV I MII/SYM RXD3 I MII/SYM RXD2 I MII/SYM RXD1 I MII/SYM RXD0 I MII MDC O MII MDIO I/O VCC -- AUI CD+ I AUI CD_ I AUI RD+ I AUI RD_ I VCC -- AUI TD+ O AUI TD_ O GND -- DEC21143-TD (3/4) INPUTS AUI CD_ : ATTACHMENT UNIT INTERFACE RECEIVE COLLISION DIFFERENTIAL NEGATIVE DATA AUI CD+ : ATTACHMENT UNIT INTERFACE RECEIVE COLLISION DIFFERENTIAL POSITIVE DATA AUI RD_ : ATTACHMENT UNIT INTERFACE RECEIVE DIFFERENTIAL NEGATIVE DATA AUI RD+ : ATTACHMENT UNIT INTERFACE RECEIVE DIFFERENTIAL POSITIVE DATA GNT L : BUS GRANT IDSEL : INITIALIZATION DEVICE SELECT IREF : CURRENT REFERENCE MII CLSN/SYM RXD4 : COLLISION ASSERT/SYMBOL DATA RECEIVE MII CRS/SD : CARRIER SENSE/SIGNAL DETECT MII DV : DATA VALID MII/SYM RCLK : RECEIVE CLOCK MII/SYM RXD0 - SYM RXD3 : PARALLEL RECEIVE DATA MII/SYM TCLK : TRANSMIT CLOCK PCI CLK : CLOCK RST I : RESET SR DO : SERIAL ROM DATA TCK : JTAG CLOCK TDI : JTAG DATA TMS : JTAG TEST MODE SELECT TP RD_ : TWISTED-PAIR NEGATIVE DIFFERENTIAL RECEIVE DATA TP RD+ : TWISTED-PAIR POSITIVE DIFFERENTIAL RECEIVE DATA VCAP H : CAPACITOR FOR ANALOG PHASE-LOCKED LOOP LOGIC XTAL1 : CRYSTAL OSCILLATOR OUTPUTS AUI TD_ AUI TD+ BR A0, BR A1 BR CE L CB PADS L MII MDC MII TXEN/SYM TXD4 MII/SYM TXD0 - SYM TXD3 REQ L SR CK SR CS SR DI TDO TP TD_, TP TD__ TP TD+, TP TD++ XTAL2 INPUTS/OUTPUTS ACTIV AD0 - AD31 AUI BNC BR AD0 - BR AD7 C BE L0 - C BE L3 CLKRUN L DEVSEL L FRAME L GEP0 - GEP3 LINK INT L IRDY L MII MDIO MII RX ERR/SEL10 100 PAR PERR L RCV MATCH SERR L STOP L TRDY L WAKE : : : : : : : : : : : : : : : : ATTACHMENT UNIT INTERFACE TRANSMIT DIFFERENTIAL NEGATIVE DATA ATTACHMENT UNIT INTERFACE TRANSMIT DIFFERENTIAL POSITIVE DATA BOOT ROM ADDRESS BOOT ROM OR EXTERNAL REGISTER CHIP ENABLE PCI/CARD BUS MANAGEMENT DATA CLOCK TRANSMIT ENABLE/TRANSMIT DATA PARALLEL TRANSMIT DATA BUS REQUEST SERIAL ROM CLOCK SERIAL ROM CHIP-SELECT SERIAL ROM DATA JTAG DATA TWISTED-PAIR NEGATIVE DIFFERENTIAL TRANSMIT DATA TWISTED-PAIR POSITIVE DIFFERENTIAL TRANSMIT DATA CRYSTAL OSCILLATOR : : : : : : : : : : : : : : : : : : : : : LED ACTIVITY PCI ADDRESS AND DATA BNC (10BASE2) SELECT BOOT ROM ADDRESS BUS COMMAND AND BYTE ENABLE PCI/CARD BUS CLOCK RUN INDICATION DEVICE SELECT FRAME INTERRUPT NETWORK LINK INTERRUPT REQUEST INITIATOR READY MANAGEMENT DATA INPUT/OUTPUT TRANSFERS CONTROL INFORMATION AND STATUS RECEIVE ERROR/10BASE-100BASE SELECT PARITY PARITY ERROR RECEIVE PACKET HAS PASSED SYSTEM ERROR STOP INDICATOR TARGET READY WAKE UP EVENT DEC21143-TD (4/4) BOAD CONYROL AND LEDS BOOT ROM/ EXTERNAL REGISTER PCI/CARDBUS SERIAL ROM PCI/CARDBUS INTERFACE 32 GENERALPURPOSE REGISTER 4 SERIAL ROM PORT 32 BOOT ROM PORT 32 32 DMA 32 RX FIFO 16 TX FIFO 16 RXM 1 4 WAKE-UP CONTROLLER 1 TXM 4 SIA INTERFACE NWAY 4 PHYSICAL CODING SUBLAYER (PCS) 4 SCRAMBLER/ DESCRAMBLER AUI INTERFACE 10BASE-T INTERFACE MII/SYM INTERFACE 10 Mb/s 10 Mb/s 10/100 Mb/s |
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